Job Description

Physical Design Engineer - Mixed Signal IP Join to apply for the Physical Design Engineer - Mixed Signal IP role at Qualcomm Physical Design Engineer - Mixed Signal IP 1 week ago Be among the first 25 applicants Join to apply for the Physical Design Engineer - Mixed Signal IP role at Qualcomm Company Qualcomm Technologies, Inc. Job Area Engineering Group, Engineering Group > ASICS Engineering General Summary We are looking for a physical design engineer to join our design team in San Diego California. Successful candidate will be part of design group responsible to deliver IP implementation like high-speed DDR, USB, PCI, PLL and mixed Digital and Analog designs. This person should demonstrate extensive knowledge in physical design flow and methodologies to ensure high quality and timely release, successful silicon in nanometer technologies, understand key design challenges and solutions. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Responsibilities Provide technical leadership and direction to project execution. Manage project timelines, deliverables and track them to closure. Mentor, guide and help team members in a fast-paced environment. Collaborate with design team and work with cross functional teams. Use good verbal and written communication skills to describe daily technical and non-technical issues Take responsibility for your own work and making decisions Exercise creativity to troubleshoot technical problems Requirements Bachelor’s Degree or higher in Electrical Engineering, Computer Engineering, or related fields. A minimum of 6 years’ experience in physical design engineering Successful Tapeouts in Nanometer Technologies Understanding of complex foundry design rules and requirements In-depth knowledge of design flow RTL to GDS process Floor-planning Automatic and custom placement Multi-voltage power domains Pre-placement and pre-routing Power Design Networks PDN-planning Place & Route Clock Tree Synthesis and customization Static Timing Analysis Understand Timing constraints Fixing timing violations Physical Verification

DRC, LVS, ERC, DFM

Virtuoso is a plus Experience with industry leading tools Cadence Synopsys Mentor Ansys Working knowledge of programming languages, HDL, OS Python, C++, TCL, Perl, Awk Verilog/VHDL,Unix/Linux Excellent written and verbal communication. Automation with Perl, Python and tcl is plus Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay Range And Other Compensation & Benefits $164,000.00 - $246,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers. 3076429 Seniority level Seniority level Not Applicable Employment type Employment type Full-time Job function Job function Other Industries Telecommunications Referrals increase your chances of interviewing at Qualcomm by 2x Get notified about new Physical Design Engineer jobs in San Diego, CA . Electrical Engineer, Cable and Harness Design Sr. Mechanical Engineer (Plastic and Sheet Metal design, Medical Device) Tijuana, Baja California, Mexico 13 hours ago Digital ASIC Design Engineer for High-Speed Interfaces Poway, CA $180,000.00-$200,000.00 4 days ago CPU Physical Design – Low Power Signoff Engineer Analog/Mixed Signal ASIC Design Engineer Engr 2, Quality (Must Have Risk Management, Design Control & Change Control Exp) Poway, CA $180,000.00-$200,000.00 17 hours ago CPU Physical Design Pathfinding Engineer VLSI Design Engineer for Server / Data Center Products Analog/Mixed Signal ASIC Design Engineer We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI. #J-18808-Ljbffr Qualcomm

Job Tags

Full time, Work experience placement, Work from home,

Similar Jobs